Education:

• Ph.D., Electrical Engineering, The University of Toledo ,Toledo, Ohio, 1991
• M.Tech., Electrical Engineering, Indian Institute of Technology, Madras, India, 1986
• B.Tech., Electrical Engineering, Indian Institute of Technology , Madras, India, 1984

Areas of Teaching and Research:

• Analog phenomena in digital circuits
• Analog and digital circuit design
• RF circuits
• CAD for VLSI
• VLSI testing
• RF Circuit Design
• Design Automation
• Hardware Testing
• Computer Architecture
• Embedded Systems
• Digital Electronics

Honors and Distinctions:

Selected Publications:

• A. N. Elkammar, S. R. Vemuru and N. Scheinberg. "A Bus Encoding Scheme to Reduce Power Consuming Signal Transitions". Proceedings of the International Conference on Embedded Systems and Applications. pp. 12-17. Las Vegas, NV. June 2004.
• S.R. Vemuru. "Simultaneous Switching noise Estimation Including the Effects of the Driving Transistor Gate-Source Capacitances". International Conference on VLSI. Las Vegas, NV. June 2003.
• Nathaniel Bird, Ethan Miller, Paul Pfeiffer and Srinivasa Vemuru. "channel routing with Crosstalk Considerations". Proceedings of the International Conference on VLSI. Las Vegas, NV. pp. 119-124. June 2003.
• S.R. Vemuru and O. Ogunnika, "Dual-modulus Prescalar Implementation. Proceedings of the International Conference on VLSI. Las Vegas, NV. pp. 102-106, June 2002. Using Clock Suppression"
• S. R. Vemuru, "Effects of simultaneous switching noise on tapered buffer design," IEEE Transactions on VLSI Systems, vol. 5, no. 3, pp. 290-300, September, 1997.
• S. R. Vemuru, "Accurate simultaneous switching noise estimation including velocity saturation effects," IEEE Transactions on Components, Hybrids, and Packaging-Part B: Advanced Packaging, vol 19, no. 2, pp. 344-349, May 1996.
• S. R. Vemuru, "Delay-macromodeling of CMOS transmission-gate-based circuits," International Journal of Modelling and Simulation, vol 15., no. 3, pp. 90-97, June 1995.
• S. R. Vemuru, "Split inherent-capacitive load model for CMOS buffer design," International Journal of Electronics, vol. 78, no. 2, pp. 359-365, February 1995.
• S. R. Vemuru and N. Scheinberg, "Short-circuit power dissipation estimation for CMOS logic gates," IEEE Transactions on Circuits and Systems - Part I, vol. 41, no. 11, pp. 762-765, November 1994.
• S. R. Vemuru, "Layout Comparison of MOSFETs with large W/L ratios", IEEE Electronics Letters, vol. 28, no. 25, pp. 2327-2329, 1992.
• S. R. Vemuru and E. D. Smith, "Accurate delay estimation model for lumped CMOS logic gates," IEEE Proceedings-G, vol. 138, no. 5, October 1991.
• S. R. Vemuru and A. Thorbjornsen, "Variable Taper Buffer Design," IEEE Journal of Solid-State Circuits, vol. 26, no. 9, pp. 1265-1269, September 1991